FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder

Loukil, Hassen and BELGHITH, Fatma and MASMOUDI, Nouri (2010) FPGA Design of an Intra 16 × 16 Module for H.264/AVC Video Encoder. Scientific Research, 1 (1). pp. 18-29.


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Abstract|ملخص البحث

In this paper, we propose novel hardware architecture for intra 16 × 16 module for the macroblock engine of a new video coding standard H.264. To reduce the cycle of intra prediction 16 × 16, transform/quantization, and inverse quantization/inverse transform of H.264, an advanced method for different operation is proposed. This architecture can process one macroblock in 208 cycles for all cases of macroblock type by processing 4 × 4 Hadamard transform and quantization during 16 × 16 prediction. This module was designed using VHDL Hardware Description Language (HDL) and works with a 160 MHz frequency using ALTERA NIOS-II development board with Stratix II EP2S60F1020C3 FPGA. The system also includes software running on an NIOS-II processor in order to implementing the pre-processing and the post-processing functions. Finally, the execution time of our HW solution is decreased by 26% when compared with the previous work.

Item Type|تصنيف النتاج العلمي: Article| منشور علمي
Subjects | مجال موضوع النشر: Electrical Engineering
Divisions | الكلية: College Of Engineering > Electrical Engineering
Depositing User: HASSEN LOUKIL
Date Deposited: 06 Jun 2018 12:01
Last Modified: 06 Jun 2018 12:01
URI: http://eprints.kku.edu.sa/id/eprint/3800

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